42 lines
1.1 KiB
Systemverilog
42 lines
1.1 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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`timescale 1ns / 100ps
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module main;
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real r;
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integer rc;
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time t;
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// verilator lint_off REALCVT
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initial begin
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rc = $sscanf("8.125", "%f", r); // as real
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`checkd(rc, 1);
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`checkr(r, 8.125);
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rc = $sscanf("8125", "%t", r); // in ns but round to 100 ps
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`checkd(rc, 1);
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t = r;
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`checkr(t, 813);
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$timeformat(-3, 2, "ms", 10);
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rc = $sscanf("8.125", "%t", r); // in ms
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`checkd(rc, 1);
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t = r;
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`checkr(t, 8125000);
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$finish;
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end
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endmodule
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