20 lines
467 B
Systemverilog
20 lines
467 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic signed [64:0] i_x,
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output logic signed [64:0] o_y
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);
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struct {logic signed [64:0] m_x;} s;
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assign s.m_x = i_x;
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assign o_y = -s.m_x;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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