22 lines
419 B
Systemverilog
22 lines
419 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef t1_t;
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typedef struct packed {
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t1_t x; // <--- Bad: Circular
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} t2_t;
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typedef t2_t [1:0] t3_t;
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typedef t3_t t1_t; // <--- Bad: Circular (or above)
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t1_t x;
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endmodule
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