verilator/test_regress/t/t_strength_strong1_strong1_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0

module t;
   wire (strong1, strong1) a = 1;
   initial begin
      $stop;
   end

endmodule