34 lines
912 B
Systemverilog
34 lines
912 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2023 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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module t(/*AUTOARG*/);
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initial begin
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int o;
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int i;
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o = 0;
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i = 0;
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randsequence(main)
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main : recurse recurse;
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recurse: { i++; if ((i % 4) == 0) break; } add recurse;
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add: { o++; } ;
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endsequence
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`checkd(o, 3);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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