2025-03-27 16:10:48 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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`verilator_config
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hier_workers -module "Test" -workers 2
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2025-07-10 10:56:14 +02:00
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hier_block -module "Check"
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hier_workers -module "Check" -workers 2
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2025-09-13 16:19:00 +02:00
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hier_block -module "CoreHier"
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hier_workers -module "CoreHier" -workers 2
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