verilator/test_regress/t/t_opt_expand_keep_widths.out

[0] in5=0 clock_10=0 clock_12=0 out18=1
[5] in5=0 clock_10=0 clock_12=1 out18=1
[10] in5=0 clock_10=0 clock_12=0 out18=1
[15] in5=0 clock_10=1 clock_12=0 out18=1
[15] in5=0 clock_10=1 clock_12=0 out18=0
[20] in5=0 clock_10=0 clock_12=0 out18=0
*-* All Finished *-*
Preserve C++ widths in V3Expand (#5975) During V3Expand, some w32/1 (width == 32, widthMin == 1), nodes (e.g.: RedOr) are replaced with w1 nodes (width == widthMin == 1) (e.g.: Neq). However, V3Expand runs after V3Clean, when we are in C++ width world, so we need to preserve the width/widthMin distinction, otherwise a later constant folding can eliminate e.g. a necessary AstAnd used clear an intermediate result (isAllOnes is true for a Const 1 with w1, but false for a Const 1 with w32/1). Attempting to fix by preserving all width/widthMin during a replacement in V3Expand. DFG itself is fine, but the transformed code hits the above. Fixes #5953 2025-05-04 17:31:27 +02:00			`[0] in5=0 clock_10=0 clock_12=0 out18=1`
			`[5] in5=0 clock_10=0 clock_12=1 out18=1`
			`[10] in5=0 clock_10=0 clock_12=0 out18=1`
			`[15] in5=0 clock_10=1 clock_12=0 out18=1`
			`[15] in5=0 clock_10=1 clock_12=0 out18=0`
			`[20] in5=0 clock_10=0 clock_12=0 out18=0`
			`- All Finished -`