23 lines
385 B
Systemverilog
23 lines
385 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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integer top;
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task x;
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output top;
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begin end
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endtask
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initial begin
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begin: lower
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integer top;
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end
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end
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endmodule
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