verilator/test_regress/t/t_lint_nolatch_bad.out

%Warning-NOLATCH: t/t_lint_nolatch_bad.v:12:4: No latches detected in always_latch block
   12 |    always_latch
      |    ^~~~~~~~~~~~
                  ... For warning description see https://verilator.org/warn/NOLATCH?v=latest
                  ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message.
%Error: Exiting due to
Cleanup missing copyrights and those on simply copied files. No functional change. 2023-01-21 02:42:30 +01:00			`%Warning-NOLATCH: t/t_lint_nolatch_bad.v:12:4: No latches detected in always_latch block`
			`12 \| always_latch`
Add LATCH and NOLATCH warnings (#1609) (#2740). 2021-01-05 20:26:01 +01:00			`\| ^~~~~~~~~~~~`
IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 17:03:32 +02:00			`... For warning description see https://verilator.org/warn/NOLATCH?v=latest`
			`... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message.`
Add LATCH and NOLATCH warnings (#1609) (#2740). 2021-01-05 20:26:01 +01:00			`%Error: Exiting due to`