2017-04-27 00:34:01 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
|
|
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
|
|
|
|
// without warranty, 2017 by Todd Strader.
|
2020-03-21 16:24:24 +01:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
2017-04-27 00:34:01 +02:00
|
|
|
|
|
|
|
|
module t (
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
localparam the_localparam = 8'd256;
|
|
|
|
|
|
|
|
|
|
endmodule
|