20 lines
396 B
Systemverilog
20 lines
396 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module for Issue#1609
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input a,
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output reg o
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);
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always_comb begin
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// verilator lint_off CASEINCOMPLETE
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case (a)
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1'b0: o = 1;
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endcase
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end
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endmodule
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