24 lines
452 B
Systemverilog
24 lines
452 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (
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lhs,
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o
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);
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input wire [7:0] lhs;
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output reg [7:0] o;
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wire [7:0] shifted;
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always @(shifted or lhs) begin
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if (lhs[7]) o = shifted ^ 8'h1b;
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else o = shifted;
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end
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assign shifted = lhs << 1;
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endmodule
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