verilator/test_regress/t/t_lint_blkseq_bad.out

%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:22:14: Blocking assignment '=' in sequential logic process
                                            : ... note: In instance 't'
                                            : ... Suggest using delayed assignment '<='
   22 |     sync_blk = 1'b1;
      |              ^
                 ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest
                 ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message.
%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:23:15: Blocking assignment '=' in sequential logic process
                                            : ... note: In instance 't'
                                            : ... Suggest using delayed assignment '<='
   23 |     sync_blk2 = 1'b1;   
      |               ^
%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:66:29: Blocking assignment '=' in sequential logic process
                                            : ... note: In instance 't.a'
                                            : ... Suggest using delayed assignment '<='
   66 |   always @(posedge clk) out = 1;
      |                             ^
%Warning-BLKSEQ: t/t_lint_blkseq_bad.v:75:29: Blocking assignment '=' in sequential logic process
                                            : ... note: In instance 't.b'
                                            : ... Suggest using delayed assignment '<='
   75 |   always @(posedge clk) out = 1;
      |                             ^
%Warning-COMBDLY: t/t_lint_blkseq_bad.v:29:16: Non-blocking assignment '<=' in combinational logic process
                                             : ... This will be executed as a blocking assignment '='!
   29 |     combo_nblk <= 1'b1;
      |                ^~
                  ... For warning description see https://verilator.org/warn/COMBDLY?v=latest
                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
                  *** See https://verilator.org/warn/COMBDLY?v=latest before disabling this,
                  else you may end up with different sim results.
%Error: Exiting due to