25 lines
463 B
Systemverilog
25 lines
463 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Anthony Donlon.
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// SPDX-License-Identifier: CC0-1.0
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module sub # (
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parameter PARAM_A = 1,
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parameter type PARAM_B = logic
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) (
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input pin_1
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);
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endmodule
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module t;
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parameter type PARAM_B = string;
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sub #(
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.PARAM_B(PARAM_B),
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.pin_1(1)
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) i_sub (
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.PARAM_A(1)
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);
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endmodule
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