15 lines
1.0 KiB
Plaintext
15 lines
1.0 KiB
Plaintext
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%Error: t/t_gate_width_bad.v:14:26: Gate primitive connection expects 1 bits on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6)
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: ... note: In instance 't'
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14 | buf buf2[0:0] (out[1], 2'b01);
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| ^~~~~
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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%Error: t/t_gate_width_bad.v:15:28: Gate primitive connection expects 1 bits on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6)
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: ... note: In instance 't'
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15 | buf buf3[0:0] (out[2], in[1:0]);
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| ^
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%Error: t/t_gate_width_bad.v:16:28: Gate primitive connection expects 4 bits or 1 bit on the gate port, but the connection generates 2 bits (IEEE 1800-2023 28.3.6)
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: ... note: In instance 't'
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16 | buf buf4[3:0] (out[2], in[1:0]);
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| ^
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%Error: Exiting due to
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