29 lines
567 B
Systemverilog
29 lines
567 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class base;
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function new(string name);
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$display(name);
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if(name == "42") $finish;
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endfunction
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function string retstr();
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return $sformatf("%0d", $c("42"));
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endfunction
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endclass
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class derived extends base;
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function new();
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super.new(retstr());
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endfunction
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endclass
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module t;
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initial begin
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derived test = new;
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end
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endmodule
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