2024-04-28 18:52:25 +02:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
|
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
|
|
|
// any use, without warranty, 2024 by Wilson Snyder.
|
|
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
|
|
2025-09-13 15:28:43 +02:00
|
|
|
module t;
|
2024-04-28 18:52:25 +02:00
|
|
|
|
|
|
|
|
event e1;
|
|
|
|
|
|
|
|
|
|
initial begin
|
|
|
|
|
e1.bad_method();
|
|
|
|
|
end
|
|
|
|
|
|
|
|
|
|
endmodule
|