verilator/test_regress/t/t_config_include_bad.v

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2025-05-01 01:00:17 +02:00
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
include "meant_to_tick_include.v"
module t;
endmodule