53 lines
1.0 KiB
Systemverilog
53 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Based on icarus/ivtest/ivltests/sv_class_super6.v
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class B;
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int m_x, m_y;
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task set_y;
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m_y = 2000;
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endtask
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function void check_x;
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`checkd(m_x, 1000);
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endfunction
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endclass
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class C extends B;
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byte m_x, m_y;
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task set_x;
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m_x = 6;
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this.m_y = 7;
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this.super.m_x = 1000;
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endtask
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function void check_y;
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`checkd(m_x, 6);
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`checkd(this.m_y, 7);
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`checkd(this.super.m_y, 2000);
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endfunction
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endclass
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module test;
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C c;
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initial begin
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c = new;
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c.set_x();
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c.set_y();
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c.check_x();
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c.check_y();
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$finish;
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end
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endmodule
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