2024-03-02 15:06:54 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsDef;
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int imembera;
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function new(default);
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imembera = i + 1;
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endfunction
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endclass
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class ClsDefFwd;
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int imembera;
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extern function new(default);
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endclass
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function ClsDefFwd::new(default);
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endfunction
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2025-09-13 15:28:43 +02:00
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module t;
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2024-03-02 15:06:54 +01:00
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initial begin
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// TODO real test
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$stop;
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end
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endmodule
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