49 lines
975 B
Systemverilog
49 lines
975 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pk1;
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typedef struct packed {
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int AddrBits;
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int DataBits;
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} cfg_t;
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endpackage
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virtual class a_class_t #(
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parameter pk1::cfg_t CFG = 0
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);
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// verilator lint_off ASCRANGE
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localparam type addr_t = logic [CFG.AddrBits-1:0];
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localparam type data_t = logic [CFG.DataBits-1:0];
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// verilator lint_on ASCRANGE
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typedef struct packed {
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addr_t addr;
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data_t data;
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} pkt_t;
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endclass
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interface ifc #(
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parameter pk1::cfg_t CFG = 0
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);
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a_class_t #(CFG)::pkt_t p;
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endinterface
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module a_to_b #(
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parameter pk1::cfg_t ACFG = 0
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) (
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ifc bus
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);
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// sturf
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endmodule
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module t;
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localparam pk1::cfg_t ACFG = '{AddrBits : 64, DataBits : 64};
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ifc #(.CFG(ACFG)) the_bus ();
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a_to_b #(ACFG) a_to_b (.bus(the_bus));
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endmodule
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