24 lines
536 B
Systemverilog
24 lines
536 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class C;
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task static task_st(int x); // BAD - methods have automatic lifetime
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int y;
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y = 2 * x;
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endtask
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function static int func_st(int x); // BAD - methods have automatic lifetime
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int y;
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y = 2 * x;
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return y;
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endfunction
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endclass
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initial $stop;
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endmodule
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