57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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int callCount = 0;
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int callCount2 = 0;
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int value = 6;
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bit[5:0] value2 = 6;
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function int get();
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callCount += 1;
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return value;
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endfunction
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function bit[5:0] get2();
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callCount2 += 1;
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return value2;
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endfunction
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function int getPure();
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return callCount2;
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endfunction
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endclass
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module t;
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Cls c;
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initial begin
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bit called = 0;
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c = new;
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case (c.get())
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4: $stop;
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5: $stop;
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6: called = 1;
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7: $stop;
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default: $stop;
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endcase
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if (!called) $stop;
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if (c.callCount != 1) $stop;
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called = 0;
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case (c.get2())
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4: $stop;
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5: $stop;
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6: called = 1;
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7: $stop;
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default: $stop;
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endcase
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case (c.getPure())
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1:;
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default: $stop;
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endcase
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if (!called) $stop;
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if (c.callCount2 != 1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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