2024-10-08 01:14:41 +02:00
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%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
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2023-09-23 14:52:50 +02:00
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: ... note: In instance 't'
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2024-10-08 01:14:41 +02:00
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16 | assign a = b[0];
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2020-04-04 02:07:46 +02:00
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| ^
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2025-04-05 23:10:28 +02:00
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... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
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2019-05-03 00:45:32 +02:00
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%Error: Exiting due to
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