verilator/test_regress/t/t_bitsel_const_bad.out

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2024-10-08 01:14:41 +02:00
%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
: ... note: In instance 't'
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16 | assign a = b[0];
| ^
... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
%Error: Exiting due to