24 lines
479 B
Systemverilog
24 lines
479 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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a, clk
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);
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input a;
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input clk;
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function logic func(input logic i);
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return i;
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endfunction
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global clocking @(posedge clk);
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endclocking
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assert property (@(posedge clk) $future_gclk(a) == func(a));
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endmodule
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