46 lines
927 B
Systemverilog
46 lines
927 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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interface INTF;
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logic x;
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logic y;
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logic z;
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endinterface
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class Dummy;
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virtual INTF vif;
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function new(virtual INTF vif);
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this.vif = vif;
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endfunction
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endclass
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module t_virtual_interface_member_trigger();
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logic s1, src_val;
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logic s2;
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INTF vintf();
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assign vintf.x = s1;
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assign vintf.y = src_val;
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assign vintf.z = !vintf.y;
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assign s2 = vintf.z;
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assign s1 = s2;
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Dummy d;
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initial begin
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d = new(vintf);
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#1ns;
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src_val = 0;
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#1ns;
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if (!(d.vif.x == 1 && d.vif.y == 0 && d.vif.z == 1 && s1 == 1 && s2 == 1)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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