16 lines
435 B
Systemverilog
16 lines
435 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int array_bad[0]; // <--- Error: Must be positive size
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int array2_bad[-1]; // <--- Error: Must be positive size
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sub #(1) u_sub();
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endmodule
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module sub #(parameter SIZE=0);
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int ignore[SIZE];
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endmodule
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