2011-02-15 01:25:30 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2026-01-27 02:24:34 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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2020-03-21 16:24:24 +01:00
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// SPDX-License-Identifier: CC0-1.0
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2011-02-15 01:25:30 +01:00
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2025-09-13 15:28:43 +02:00
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module t;
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2011-02-15 01:25:30 +01:00
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initial begin
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2019-03-10 19:57:01 +01:00
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// verilator lint_off IGNOREDRETURN
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2011-02-15 01:25:30 +01:00
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func(0, 1'b1);
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end
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function automatic int func
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(
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input int a,
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output bit b );
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return 0;
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endfunction
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endmodule
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