27 lines
587 B
Systemverilog
27 lines
587 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [3:0] ia = 4'd1;
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wire signed [3:0] iufunc;
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// verilator lint_off WIDTH
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assign #1 iufunc = int_func(ia);
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// verilator lint_on WIDTH
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function [31:0] int_func;
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input [31:0] in;
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int_func = in * 2;
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endfunction
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initial begin
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#1
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if (iufunc != 4'd2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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