19 lines
539 B
Systemverilog
19 lines
539 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t #(
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parameter NUM_LANES = 1);
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reg [(NUM_LANES*8)-1:0] link_data_reg, link_data_reg_in;
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reg [1:0] other;
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always @(*) begin
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if (NUM_LANES >= 2) begin // Not a generate if
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link_data_reg_in = {{((NUM_LANES - 2) * 8) {1'b0}}, link_data_reg[15:8]};
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end
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other = {32'bz{1'b1}};
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end
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endmodule
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