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#!/usr/bin/env python3
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2006-08-26 11:35:28 +00:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2024-01-01 03:19:59 -05:00
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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2020-03-21 11:24:24 -04:00
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# can redistribute it and/or modify it under the terms of either the GNU
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2009-05-04 17:07:57 -04:00
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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2020-03-21 11:24:24 -04:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 11:35:28 +00:00
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2024-09-08 13:00:03 -04:00
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import vltest_bootstrap
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2018-05-07 20:42:28 -04:00
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2024-09-08 13:00:03 -04:00
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test.scenarios('simulator')
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2006-08-26 11:35:28 +00:00
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2024-09-08 13:00:03 -04:00
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test.compile(v_flags2=["--stats -fno-dfg"])
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2006-08-26 11:35:28 +00:00
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2024-09-08 13:00:03 -04:00
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test.execute()
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if test.vlt_all:
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test.file_grep(test.stats, r'Optimizations, Gate assign merged\s+(\d+)', 28)
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test.passes()
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