22 lines
600 B
Systemverilog
22 lines
600 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2025 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t;
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initial begin
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randsequence()
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main : first := 1 { $stop; } | second := 0;
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first : { $display("first"); };
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second : { $display("second"); };
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endsequence
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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