20 lines
548 B
Systemverilog
20 lines
548 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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// Test config allows selecting two different libraries for these instances
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m1 u_1();
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m2 u_2();
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final $write("*-* All Finished *-*\n");
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endmodule
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config cfg1;
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design t;
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// Use libb's version of m3 for m1 and liba's version of m3 for m2
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cell liba.m3 liblist libb;
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cell libb.m3 use liba.m3;
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endconfig
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