31 lines
727 B
Systemverilog
31 lines
727 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef int T;
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module test ( /*AUTOARG*/
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// Outputs
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bad1, bad2, bad3, bad4, bad5
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);
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output [15:0] bad1;
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shortint bad1; // <--- Error (type doesn't match above)
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output [31:0] bad2;
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T bad2; // <--- Error (type doesn't match above due to range)
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output [3:0] bad3;
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reg [7:0] bad3; // <--- Error (range doesn't match)
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output bad4;
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reg bad4;
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reg bad4; // <--- Error (duplicate)
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output bad5;
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output bad5; // <--- Error (duplicate)
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reg bad5; // <--- Error (duplicate)
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endmodule
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