19 lines
421 B
Systemverilog
19 lines
421 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int m_dyn_arr[];
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rand int m_unp_arr[10];
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endclass
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module t;
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initial begin
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Packet p = new;
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p.m_dyn_arr[0].rand_mode(0);
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p.m_unp_arr[0].rand_mode(0);
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end
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endmodule
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