37 lines
630 B
Systemverilog
37 lines
630 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Cls;
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rand int m_x;
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int m_y = -1;
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endclass
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function int func1(Cls obj, int y);
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return obj.randomize() with (
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m_x) {
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m_x > 0;
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m_x < y;
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};
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endfunction
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function int func2(Cls obj, int y);
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return obj.randomize() with (
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m_x) {
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m_x > 0;
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m_x < m_y;
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};
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endfunction
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module t;
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initial begin
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Cls c;
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int i;
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c = new;
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i = func1(c, 2);
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i = func2(c, 2);
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end
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endmodule
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