33 lines
1.2 KiB
Python
33 lines
1.2 KiB
Python
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('vlt_all')
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test.top_filename = "t/t_hier_block.v"
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# stats will be deleted but generation will be skipped if libs of hierarchical blocks exist.
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test.clean_objs()
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test.compile(verilator_flags2=[
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't/t_hier_block.cpp', '--stats', '--hierarchical', '--Wno-TIMESCALEMOD', '--CFLAGS',
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'"-pipe -DCPP_MACRO=cplusplus"', '--binary'
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])
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test.execute()
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test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^\s+\/\/\s+timeprecision\s+(\d+)ps;', 1)
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test.file_grep(test.obj_dir + "/Vsub0/sub0.sv", r'^module\s+(\S+)\s+', "sub0")
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test.file_grep(test.obj_dir + "/Vsub1/sub1.sv", r'^module\s+(\S+)\s+', "sub1")
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test.file_grep(test.obj_dir + "/Vsub2/sub2.sv", r'^module\s+(\S+)\s+', "sub2")
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test.file_grep(test.stats, r'HierBlock,\s+Hierarchical blocks\s+(\d+)', 14)
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test.file_grep(test.run_log_filename, r'MACRO:(\S+) is defined', "cplusplus")
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test.passes()
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