23 lines
349 B
Coq
23 lines
349 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Wilson Snyder.
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module t
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(
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input wire clk,
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input wire a
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);
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integer q;
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always @ (a or posedge clk)
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begin
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if (a)
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q = 0;
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else
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q = q + 1;
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end
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endmodule
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