41 lines
1.2 KiB
Systemverilog
41 lines
1.2 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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initial begin
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bit arr[];
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bit [1:0] arr2[$];
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bit [4:0] arr5[];
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bit [5:0] arr6[$];
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string v;
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bit [5:0] bit6 = 6'b111000;
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{ >> bit {arr}} = bit6;
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v = $sformatf("%p", arr); `checks(v, "'{'h0, 'h0, 'h0, 'h1, 'h1, 'h1} ");
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{ << bit {arr}} = bit6;
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v = $sformatf("%p", arr); `checks(v, "'{'h1, 'h1, 'h1, 'h0, 'h0, 'h0} ");
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{ >> bit[1:0] {arr2}} = bit6;
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v = $sformatf("%p", arr2); `checks(v, "'{'h0, 'h2, 'h3} ");
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{ << bit[1:0] {arr2}} = bit6;
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v = $sformatf("%p", arr2); `checks(v, "'{'h3, 'h2, 'h0} ");
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{ >> bit [5:0] {arr6} } = bit6;
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v = $sformatf("%p", arr6); `checks(v, "'{'h38} ");
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{ << bit [5:0] {arr6} } = bit6;
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v = $sformatf("%p", arr6); `checks(v, "'{'h38} ");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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