2017-11-18 23:42:35 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 16:24:24 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2017-11-18 23:42:35 +01:00
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2024-10-08 01:14:41 +02:00
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module t (/*AUTOARG*/);
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2017-11-18 23:42:35 +01:00
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looped looped ();
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endmodule
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module looped (/*AUTOARG*/);
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looped looped ();
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endmodule
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