Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Convert AstModule to DfgGraph
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2022 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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//
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// Convert and AstModule to a DfgGraph. We proceed by visiting convertable logic blocks (e.g.:
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// AstAssignW of appropriate type and with no delays), recursively constructing DfgVertex instances
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// for the expressions that compose the subject logic block. If all expressions in the current
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// logic block can be converted, then we delete the logic block (now represented in the DfgGraph),
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// and connect the corresponding DfgVertex instances appropriately. If some of the expressions were
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// not convertible in the current logic block, we revert (delete) the DfgVertex instances created
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// for the logic block, and leave the logic block in the AstModule. Any variable reference from
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// non-converted logic blocks (or other constructs under the AstModule) are marked as being
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// referenced in the AstModule, which is relevant for later optimization.
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//
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//*************************************************************************
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#include "config_build.h"
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#include "verilatedos.h"
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#include "V3Ast.h"
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#include "V3Dfg.h"
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#include "V3DfgPasses.h"
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#include "V3Error.h"
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#include "V3Global.h"
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VL_DEFINE_DEBUG_FUNCTIONS;
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namespace {
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// Create a DfgVertex out of a AstNodeMath. For most AstNodeMath subtypes, this can be done
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// automatically. For the few special cases, we provide specializations below
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template <typename Vertex>
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Vertex* makeVertex(const AstForDfg<Vertex>* nodep, DfgGraph& dfg) {
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return new Vertex{dfg, nodep->fileline(), DfgVertex::dtypeFor(nodep)};
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}
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//======================================================================
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// Currently unhandled nodes
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// LCOV_EXCL_START
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// AstCCast changes width, but should not exists where DFG optimization is currently invoked
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template <>
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DfgCCast* makeVertex<DfgCCast>(const AstCCast*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on strings which we don't optimize anyway
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template <>
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DfgAtoN* makeVertex<DfgAtoN>(const AstAtoN*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on strings which we don't optimize anyway
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template <>
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DfgCompareNN* makeVertex<DfgCompareNN>(const AstCompareNN*, DfgGraph&) {
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return nullptr;
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}
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// Unhandled in DfgToAst, but also operates on unpacked arrays which we don't optimize anyway
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template <>
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DfgSliceSel* makeVertex<DfgSliceSel>(const AstSliceSel*, DfgGraph&) {
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return nullptr;
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}
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// LCOV_EXCL_STOP
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} // namespace
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class AstToDfgVisitor final : public VNVisitor {
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// NODE STATE
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// AstNode::user1p // DfgVertex for this AstNode
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const VNUser1InUse m_user1InUse;
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// STATE
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DfgGraph* const m_dfgp; // The graph being built
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V3DfgOptimizationContext& m_ctx; // The optimization context for stats
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bool m_foundUnhandled = false; // Found node not implemented as DFG or not implemented 'visit'
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std::vector<DfgVertex*> m_uncommittedVertices; // Vertices that we might decide to revert
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2022-09-26 15:21:05 +02:00
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bool m_converting = false; // We are trying to convert some logic at the moment
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2022-09-27 01:06:50 +02:00
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std::vector<DfgVarPacked*> m_varPackedps; // All the DfgVarPacked vertices we created.
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std::vector<DfgVarArray*> m_varArrayps; // All the DfgVarArray vertices we created.
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Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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// METHODS
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void markReferenced(AstNode* nodep) {
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nodep->foreach<AstVarRef>([this](const AstVarRef* refp) {
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// No need to (and in fact cannot) mark variables with unsupported dtypes
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if (!DfgVertex::isSupportedDType(refp->varp()->dtypep())) return;
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getNet(refp->varp())->setHasModRefs();
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});
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}
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void commitVertices() { m_uncommittedVertices.clear(); }
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void revertUncommittedVertices() {
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for (DfgVertex* const vtxp : m_uncommittedVertices) vtxp->unlinkDelete(*m_dfgp);
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m_uncommittedVertices.clear();
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}
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2022-09-27 01:06:50 +02:00
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DfgVertexLValue* getNet(AstVar* varp) {
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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if (!varp->user1p()) {
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2022-09-27 01:06:50 +02:00
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// Note DfgVertexLValue vertices are not added to m_uncommittedVertices, because we
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// want to hold onto them via AstVar::user1p, and the AstVar might be referenced via
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// multiple AstVarRef instances, so we will never revert a DfgVertexLValue once
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2022-09-30 12:35:03 +02:00
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// created. We will delete unconnected variable vertices at the end.
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2022-09-27 01:06:50 +02:00
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if (VN_IS(varp->dtypep()->skipRefp(), UnpackArrayDType)) {
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DfgVarArray* const vtxp = new DfgVarArray{*m_dfgp, varp};
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varp->user1p();
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m_varArrayps.push_back(vtxp);
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varp->user1p(vtxp);
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} else {
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DfgVarPacked* const vtxp = new DfgVarPacked{*m_dfgp, varp};
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m_varPackedps.push_back(vtxp);
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varp->user1p(vtxp);
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}
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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}
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2022-09-27 01:06:50 +02:00
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return varp->user1u().to<DfgVertexLValue*>();
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Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
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}
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DfgVertex* getVertex(AstNode* nodep) {
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DfgVertex* vtxp = nodep->user1u().to<DfgVertex*>();
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UASSERT_OBJ(vtxp, nodep, "Missing Dfg vertex");
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return vtxp;
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}
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// Returns true if the expression cannot (or should not) be represented by DFG
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bool unhandled(AstNodeMath* nodep) {
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// Short-circuiting if something was already unhandled
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if (!m_foundUnhandled) {
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// Impure nodes cannot be represented
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if (!nodep->isPure()) {
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m_foundUnhandled = true;
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++m_ctx.m_nonRepImpure;
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}
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// Check node has supported dtype
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if (!DfgVertex::isSupportedDType(nodep->dtypep())) {
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m_foundUnhandled = true;
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++m_ctx.m_nonRepDType;
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}
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}
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return m_foundUnhandled;
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}
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2022-09-25 17:03:15 +02:00
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// Build DfgEdge representing the LValue assignment. Returns false if unsuccessful.
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bool convertAssignment(FileLine* flp, AstNode* nodep, DfgVertex* vtxp) {
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if (AstVarRef* const vrefp = VN_CAST(nodep, VarRef)) {
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m_foundUnhandled = false;
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visit(vrefp);
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if (m_foundUnhandled) return false;
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2022-09-27 01:06:50 +02:00
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getVertex(vrefp)->as<DfgVarPacked>()->addDriver(flp, 0, vtxp);
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2022-09-25 17:03:15 +02:00
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return true;
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}
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if (AstSel* const selp = VN_CAST(nodep, Sel)) {
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AstVarRef* const vrefp = VN_CAST(selp->fromp(), VarRef);
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2022-09-27 01:06:50 +02:00
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const AstConst* const lsbp = VN_CAST(selp->lsbp(), Const);
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2022-09-25 17:03:15 +02:00
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if (!vrefp || !lsbp || !VN_IS(selp->widthp(), Const)) {
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++m_ctx.m_nonRepLhs;
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return false;
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}
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m_foundUnhandled = false;
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visit(vrefp);
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if (m_foundUnhandled) return false;
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2022-09-27 01:06:50 +02:00
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getVertex(vrefp)->as<DfgVarPacked>()->addDriver(flp, lsbp->toUInt(), vtxp);
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return true;
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}
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if (AstArraySel* const selp = VN_CAST(nodep, ArraySel)) {
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AstVarRef* const vrefp = VN_CAST(selp->fromp(), VarRef);
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const AstConst* const idxp = VN_CAST(selp->bitp(), Const);
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|
|
|
if (!vrefp || !idxp) {
|
|
|
|
|
++m_ctx.m_nonRepLhs;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
m_foundUnhandled = false;
|
|
|
|
|
visit(vrefp);
|
|
|
|
|
if (m_foundUnhandled) return false;
|
|
|
|
|
getVertex(vrefp)->as<DfgVarArray>()->addDriver(flp, idxp->toUInt(), vtxp);
|
2022-09-25 17:03:15 +02:00
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
if (AstConcat* const concatp = VN_CAST(nodep, Concat)) {
|
|
|
|
|
AstNode* const lhsp = concatp->lhsp();
|
|
|
|
|
AstNode* const rhsp = concatp->rhsp();
|
|
|
|
|
const uint32_t lWidth = lhsp->width();
|
|
|
|
|
const uint32_t rWidth = rhsp->width();
|
|
|
|
|
|
|
|
|
|
{
|
|
|
|
|
FileLine* const lFlp = lhsp->fileline();
|
|
|
|
|
DfgSel* const lVtxp = new DfgSel{*m_dfgp, lFlp, DfgVertex::dtypeFor(lhsp)};
|
|
|
|
|
lVtxp->fromp(vtxp);
|
|
|
|
|
lVtxp->lsbp(new DfgConst{*m_dfgp, new AstConst{lFlp, rWidth}});
|
|
|
|
|
lVtxp->widthp(new DfgConst{*m_dfgp, new AstConst{lFlp, lWidth}});
|
|
|
|
|
if (!convertAssignment(flp, lhsp, lVtxp)) return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
{
|
|
|
|
|
FileLine* const rFlp = rhsp->fileline();
|
|
|
|
|
DfgSel* const rVtxp = new DfgSel{*m_dfgp, rFlp, DfgVertex::dtypeFor(rhsp)};
|
|
|
|
|
rVtxp->fromp(vtxp);
|
|
|
|
|
rVtxp->lsbp(new DfgConst{*m_dfgp, new AstConst{rFlp, 0u}});
|
|
|
|
|
rVtxp->widthp(new DfgConst{*m_dfgp, new AstConst{rFlp, rWidth}});
|
|
|
|
|
return convertAssignment(flp, rhsp, rVtxp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
++m_ctx.m_nonRepLhs;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-01 13:28:16 +02:00
|
|
|
bool convertEquation(AstNode* nodep, FileLine* flp, AstNode* lhsp, AstNode* rhsp) {
|
2022-09-25 17:03:15 +02:00
|
|
|
UASSERT_OBJ(m_uncommittedVertices.empty(), nodep, "Should not nest");
|
|
|
|
|
|
2022-09-27 01:06:50 +02:00
|
|
|
// Currently cannot handle direct assignments between unpacked types. These arise e.g.
|
|
|
|
|
// when passing an unpacked array through a module port.
|
|
|
|
|
if (!DfgVertex::isSupportedPackedDType(lhsp->dtypep())
|
|
|
|
|
|| !DfgVertex::isSupportedPackedDType(rhsp->dtypep())) {
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
++m_ctx.m_nonRepDType;
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-25 17:03:15 +02:00
|
|
|
// Cannot handle mismatched widths. Mismatched assignments should have been fixed up in
|
|
|
|
|
// earlier passes anyway, so this should never be hit, but being paranoid just in case.
|
|
|
|
|
if (lhsp->width() != rhsp->width()) { // LCOV_EXCL_START
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
++m_ctx.m_nonRepWidth;
|
|
|
|
|
return false;
|
|
|
|
|
} // LCOV_EXCL_STOP
|
|
|
|
|
|
|
|
|
|
VL_RESTORER(m_converting);
|
|
|
|
|
m_converting = true;
|
|
|
|
|
|
|
|
|
|
m_foundUnhandled = false;
|
|
|
|
|
iterate(rhsp);
|
|
|
|
|
if (m_foundUnhandled) {
|
|
|
|
|
revertUncommittedVertices();
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-01 13:28:16 +02:00
|
|
|
if (!convertAssignment(flp, lhsp, getVertex(rhsp))) {
|
2022-09-25 17:03:15 +02:00
|
|
|
revertUncommittedVertices();
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Connect the rhs vertex to the driven edge
|
|
|
|
|
commitVertices();
|
|
|
|
|
|
|
|
|
|
// Remove node from Ast. Now represented by the Dfg.
|
|
|
|
|
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
++m_ctx.m_representable;
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-27 01:06:50 +02:00
|
|
|
// Canonicalize packed variables
|
|
|
|
|
void canonicalizePacked() {
|
|
|
|
|
for (DfgVarPacked* const varp : m_varPackedps) {
|
2022-09-30 12:35:03 +02:00
|
|
|
// Delete variables with no sinks nor sources (this can happen due to reverting
|
|
|
|
|
// uncommitted vertices, which does not remove variables)
|
|
|
|
|
if (!varp->hasSinks() && varp->arity() == 0) {
|
|
|
|
|
VL_DO_DANGLING(varp->unlinkDelete(*m_dfgp), varp);
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-27 01:06:50 +02:00
|
|
|
// Gather (and unlink) all drivers
|
|
|
|
|
struct Driver {
|
|
|
|
|
FileLine* flp;
|
|
|
|
|
uint32_t lsb;
|
|
|
|
|
DfgVertex* vtxp;
|
|
|
|
|
Driver(FileLine* flp, uint32_t lsb, DfgVertex* vtxp)
|
|
|
|
|
: flp{flp}
|
|
|
|
|
, lsb{lsb}
|
|
|
|
|
, vtxp{vtxp} {}
|
|
|
|
|
};
|
|
|
|
|
std::vector<Driver> drivers;
|
|
|
|
|
drivers.reserve(varp->arity());
|
|
|
|
|
varp->forEachSourceEdge([varp, &drivers](DfgEdge& edge, size_t idx) {
|
|
|
|
|
UASSERT(edge.sourcep(), "Should not have created undriven sources");
|
|
|
|
|
drivers.emplace_back(varp->driverFileLine(idx), varp->driverLsb(idx),
|
|
|
|
|
edge.sourcep());
|
|
|
|
|
edge.unlinkSource();
|
|
|
|
|
});
|
|
|
|
|
|
|
|
|
|
// Sort drivers by LSB
|
|
|
|
|
std::stable_sort(drivers.begin(), drivers.end(),
|
|
|
|
|
[](const Driver& a, const Driver& b) { return a.lsb < b.lsb; });
|
|
|
|
|
|
|
|
|
|
// TODO: bail on multidriver
|
|
|
|
|
|
|
|
|
|
// Coalesce adjacent ranges
|
|
|
|
|
for (size_t i = 0, j = 1; j < drivers.size(); ++j) {
|
|
|
|
|
Driver& a = drivers[i];
|
|
|
|
|
Driver& b = drivers[j];
|
|
|
|
|
|
|
|
|
|
// Coalesce adjacent range
|
|
|
|
|
const uint32_t aWidth = a.vtxp->width();
|
|
|
|
|
const uint32_t bWidth = b.vtxp->width();
|
|
|
|
|
if (a.lsb + aWidth == b.lsb) {
|
|
|
|
|
const auto dtypep = DfgVertex::dtypeForWidth(aWidth + bWidth);
|
|
|
|
|
DfgConcat* const concatp = new DfgConcat{*m_dfgp, a.flp, dtypep};
|
|
|
|
|
concatp->rhsp(a.vtxp);
|
|
|
|
|
concatp->lhsp(b.vtxp);
|
|
|
|
|
a.vtxp = concatp;
|
|
|
|
|
b.vtxp = nullptr; // Mark as moved
|
|
|
|
|
++m_ctx.m_coalescedAssignments;
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
++i;
|
|
|
|
|
|
|
|
|
|
// Compact non-adjacent ranges within the vector
|
|
|
|
|
if (j != i) {
|
|
|
|
|
Driver& c = drivers[i];
|
|
|
|
|
UASSERT_OBJ(!c.vtxp, c.flp, "Should have been marked moved");
|
|
|
|
|
c = b;
|
|
|
|
|
b.vtxp = nullptr; // Mark as moved
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Reinsert sources in order
|
|
|
|
|
varp->resetSources();
|
|
|
|
|
for (const Driver& driver : drivers) {
|
|
|
|
|
if (!driver.vtxp) break; // Stop at end of cmpacted list
|
|
|
|
|
varp->addDriver(driver.flp, driver.lsb, driver.vtxp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-30 12:35:03 +02:00
|
|
|
// Canonicalize array variables
|
|
|
|
|
void canonicalizeArray() {
|
|
|
|
|
for (DfgVarArray* const varp : m_varArrayps) {
|
|
|
|
|
// Delete variables with no sinks nor sources (this can happen due to reverting
|
|
|
|
|
// uncommitted vertices, which does not remove variables)
|
|
|
|
|
if (!varp->hasSinks() && varp->arity() == 0) {
|
|
|
|
|
VL_DO_DANGLING(varp->unlinkDelete(*m_dfgp), varp);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
// VISITORS
|
|
|
|
|
void visit(AstNode* nodep) override {
|
|
|
|
|
// Conservatively treat this node as unhandled
|
2022-09-26 15:21:05 +02:00
|
|
|
if (!m_foundUnhandled && m_converting) ++m_ctx.m_nonRepUnknown;
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
m_foundUnhandled = true;
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
}
|
|
|
|
|
void visit(AstCell* nodep) override { markReferenced(nodep); }
|
|
|
|
|
void visit(AstNodeProcedure* nodep) override { markReferenced(nodep); }
|
|
|
|
|
void visit(AstVar* nodep) override {
|
|
|
|
|
// No need to (and in fact cannot) handle variables with unsupported dtypes
|
|
|
|
|
if (!DfgVertex::isSupportedDType(nodep->dtypep())) return;
|
|
|
|
|
// Mark ports as having external references
|
|
|
|
|
if (nodep->isIO()) getNet(nodep)->setHasExtRefs();
|
|
|
|
|
// Mark variables that are the target of a hierarchical reference
|
|
|
|
|
// (these flags were set up in DataflowPrepVisitor)
|
|
|
|
|
if (nodep->user2()) getNet(nodep)->setHasExtRefs();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(AstAssignW* nodep) override {
|
2022-09-26 15:21:05 +02:00
|
|
|
++m_ctx.m_inputEquations;
|
|
|
|
|
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
// Cannot handle assignment with timing control yet
|
|
|
|
|
if (nodep->timingControlp()) {
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
++m_ctx.m_nonRepTiming;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
2022-10-01 13:28:16 +02:00
|
|
|
convertEquation(nodep, nodep->fileline(), nodep->lhsp(), nodep->rhsp());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(AstAlways* nodep) override {
|
|
|
|
|
// Ignore sequential logic, or if there are multiple statements
|
|
|
|
|
const VAlwaysKwd kwd = nodep->keyword();
|
|
|
|
|
if (nodep->sensesp() || !nodep->isJustOneBodyStmt()
|
|
|
|
|
|| (kwd != VAlwaysKwd::ALWAYS && kwd != VAlwaysKwd::ALWAYS_COMB)) {
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
AstNode* const stmtp = nodep->stmtsp();
|
|
|
|
|
|
|
|
|
|
if (AstAssign* const assignp = VN_CAST(stmtp, Assign)) {
|
|
|
|
|
++m_ctx.m_inputEquations;
|
|
|
|
|
if (assignp->timingControlp()) {
|
|
|
|
|
markReferenced(stmtp);
|
|
|
|
|
++m_ctx.m_nonRepTiming;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
convertEquation(nodep, assignp->fileline(), assignp->lhsp(), assignp->rhsp());
|
|
|
|
|
} else if (AstIf* const ifp = VN_CAST(stmtp, If)) {
|
|
|
|
|
// Will only handle single assignments to the same LHS in both branches
|
|
|
|
|
AstAssign* const thenp = VN_CAST(ifp->thensp(), Assign);
|
|
|
|
|
AstAssign* const elsep = VN_CAST(ifp->elsesp(), Assign);
|
|
|
|
|
if (!thenp || !elsep || thenp->nextp() || elsep->nextp()
|
|
|
|
|
|| !thenp->lhsp()->sameTree(elsep->lhsp())) {
|
|
|
|
|
markReferenced(stmtp);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
++m_ctx.m_inputEquations;
|
|
|
|
|
if (thenp->timingControlp() || elsep->timingControlp()) {
|
|
|
|
|
markReferenced(stmtp);
|
|
|
|
|
++m_ctx.m_nonRepTiming;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Create a conditional for the rhs by borrowing the components from the AstIf
|
|
|
|
|
AstCond* const rhsp = new AstCond{ifp->fileline(), //
|
|
|
|
|
ifp->condp()->unlinkFrBack(), //
|
|
|
|
|
thenp->rhsp()->unlinkFrBack(), //
|
|
|
|
|
elsep->rhsp()->unlinkFrBack()};
|
|
|
|
|
|
|
|
|
|
if (!convertEquation(nodep, ifp->fileline(), thenp->lhsp(), rhsp)) {
|
|
|
|
|
// Failed to convert. Mark 'rhsp', as 'convertEquation' only marks 'nodep'.
|
|
|
|
|
markReferenced(rhsp);
|
|
|
|
|
// Put the AstIf back together
|
|
|
|
|
ifp->condp(rhsp->condp()->unlinkFrBack());
|
|
|
|
|
thenp->rhsp(rhsp->thenp()->unlinkFrBack());
|
|
|
|
|
elsep->rhsp(rhsp->elsep()->unlinkFrBack());
|
|
|
|
|
}
|
|
|
|
|
// Delete the auxiliary conditional
|
|
|
|
|
VL_DO_DANGLING(rhsp->deleteTree(), rhsp);
|
|
|
|
|
} else {
|
|
|
|
|
markReferenced(stmtp);
|
|
|
|
|
}
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(AstVarRef* nodep) override {
|
|
|
|
|
UASSERT_OBJ(!nodep->user1p(), nodep, "Already has Dfg vertex");
|
|
|
|
|
if (unhandled(nodep)) return;
|
|
|
|
|
|
|
|
|
|
if (nodep->access().isRW() // Cannot represent read-write references
|
|
|
|
|
|| nodep->varp()->isIfaceRef() // Cannot handle interface references
|
|
|
|
|
|| nodep->varp()->delayp() // Cannot handle delayed variables
|
|
|
|
|
|| nodep->classOrPackagep() // Cannot represent cross module references
|
|
|
|
|
) {
|
|
|
|
|
markReferenced(nodep);
|
|
|
|
|
m_foundUnhandled = true;
|
|
|
|
|
++m_ctx.m_nonRepVarRef;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Sadly sometimes AstVarRef does not have the same dtype as the referenced variable
|
|
|
|
|
if (!DfgVertex::isSupportedDType(nodep->varp()->dtypep())) {
|
|
|
|
|
m_foundUnhandled = true;
|
|
|
|
|
++m_ctx.m_nonRepVarRef;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
nodep->user1p(getNet(nodep->varp()));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void visit(AstConst* nodep) override {
|
|
|
|
|
UASSERT_OBJ(!nodep->user1p(), nodep, "Already has Dfg vertex");
|
|
|
|
|
if (unhandled(nodep)) return;
|
|
|
|
|
DfgVertex* const vtxp = new DfgConst{*m_dfgp, nodep->cloneTree(false)};
|
|
|
|
|
m_uncommittedVertices.push_back(vtxp);
|
|
|
|
|
nodep->user1p(vtxp);
|
|
|
|
|
}
|
|
|
|
|
|
2022-09-27 01:06:50 +02:00
|
|
|
// The rest of the 'visit' methods are generated by 'astgen'
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
#include "V3Dfg__gen_ast_to_dfg.h"
|
|
|
|
|
|
|
|
|
|
// CONSTRUCTOR
|
|
|
|
|
explicit AstToDfgVisitor(AstModule& module, V3DfgOptimizationContext& ctx)
|
|
|
|
|
: m_dfgp{new DfgGraph{module, module.name()}}
|
|
|
|
|
, m_ctx{ctx} {
|
|
|
|
|
// Build the DFG
|
|
|
|
|
iterateChildren(&module);
|
|
|
|
|
UASSERT_OBJ(m_uncommittedVertices.empty(), &module, "Uncommitted vertices remain");
|
2022-09-25 17:03:15 +02:00
|
|
|
|
2022-09-27 01:06:50 +02:00
|
|
|
// Canonicalize variables
|
|
|
|
|
canonicalizePacked();
|
2022-09-30 12:35:03 +02:00
|
|
|
canonicalizeArray();
|
Introduce DFG based combinational logic optimizer (#3527)
Added a new data-flow graph (DFG) based combinational logic optimizer.
The capabilities of this covers a combination of V3Const and V3Gate, but
is also more capable of transforming combinational logic into simplified
forms and more.
This entail adding a new internal representation, `DfgGraph`, and
appropriate `astToDfg` and `dfgToAst` conversion functions. The graph
represents some of the combinational equations (~continuous assignments)
in a module, and for the duration of the DFG passes, it takes over the
role of AstModule. A bulk of the Dfg vertices represent expressions.
These vertex classes, and the corresponding conversions to/from AST are
mostly auto-generated by astgen, together with a DfgVVisitor that can be
used for dynamic dispatch based on vertex (operation) types.
The resulting combinational logic graph (a `DfgGraph`) is then optimized
in various ways. Currently we perform common sub-expression elimination,
variable inlining, and some specific peephole optimizations, but there
is scope for more optimizations in the future using the same
representation. The optimizer is run directly before and after inlining.
The pre inline pass can operate on smaller graphs and hence converges
faster, but still has a chance of substantially reducing the size of the
logic on some designs, making inlining both faster and less memory
intensive. The post inline pass can then optimize across the inlined
module boundaries. No optimization is performed across a module
boundary.
For debugging purposes, each peephole optimization can be disabled
individually via the -fno-dfg-peepnole-<OPT> option, where <OPT> is one
of the optimizations listed in V3DfgPeephole.h, for example
-fno-dfg-peephole-remove-not-not.
The peephole patterns currently implemented were mostly picked based on
the design that inspired this work, and on that design the optimizations
yields ~30% single threaded speedup, and ~50% speedup on 4 threads. As
you can imagine not having to haul around redundant combinational
networks in the rest of the compilation pipeline also helps with memory
consumption, and up to 30% peak memory usage of Verilator was observed
on the same design.
Gains on other arbitrary designs are smaller (and can be improved by
analyzing those designs). For example OpenTitan gains between 1-15%
speedup depending on build type.
2022-09-23 17:46:22 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
public:
|
|
|
|
|
static DfgGraph* apply(AstModule& module, V3DfgOptimizationContext& ctx) {
|
|
|
|
|
return AstToDfgVisitor{module, ctx}.m_dfgp;
|
|
|
|
|
}
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
DfgGraph* V3DfgPasses::astToDfg(AstModule& module, V3DfgOptimizationContext& ctx) {
|
|
|
|
|
return AstToDfgVisitor::apply(module, ctx);
|
|
|
|
|
}
|