36 lines
639 B
Systemverilog
36 lines
639 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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bit s[3:0] = {0, 0, 0, 0};
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initial begin
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wait (s[1]);
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s[0] = 1;
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$display("0");
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end
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initial begin
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wait (s[2]);
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s[1] = 1;
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$display("1");
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#1 $write("*-* All Finished *-*\n");
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$finish;
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end
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initial begin
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wait (s[3]);
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s[2] = 1;
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$display("2");
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end
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initial begin
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s[3] = 1;
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end
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initial #2 $stop; // timeout
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endmodule
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