39 lines
1.0 KiB
Systemverilog
39 lines
1.0 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int arr_default_scalar[4][4];
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int row[4];
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int arr_default_array[2][4];
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int arr_mixed_default[2][3];
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initial begin
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arr_default_scalar = '{default: 0};
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foreach (arr_default_scalar[i, j]) begin
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if (arr_default_scalar[i][j] != 0) $stop;
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end
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row = '{1, 2, 3, 4};
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arr_default_array = '{default: row};
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foreach (arr_default_array[i, j]) begin
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if (arr_default_array[i][j] != row[j]) $stop;
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end
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arr_mixed_default = '{0: '{0: 1, default: 3}, default: '{default: 2}};
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if (arr_mixed_default[0][0] != 1) $stop;
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if (arr_mixed_default[0][1] != 3) $stop;
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if (arr_mixed_default[0][2] != 3) $stop;
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if (arr_mixed_default[1][0] != 2) $stop;
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if (arr_mixed_default[1][1] != 2) $stop;
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if (arr_mixed_default[1][2] != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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