52 lines
1.4 KiB
Systemverilog
52 lines
1.4 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// 6.21 Scope and lifetime
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// Automatic variables and elements of dynamically sized array variables shall
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// not be written with nonblocking, continuous, or procedural continuous
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// assignments. Non-static class properties shall not be written with continuous
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// or procedural continuous assignments.
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class Cls;
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static int s_ok1;
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static int s_ok2;
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int m_bad1;
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int m_bad2;
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endclass
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module t(clk);
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input clk;
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Cls c;
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automatic int bad_auto3;
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automatic int bad_auto4;
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int bad_dyn5[];
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int bad_dyn6[];
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int empty_dyn[];
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assign bad_auto3 = 2; // <--- Error: continuous automatic
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assign bad_dyn5 = empty_dyn; // <--- Error: continuous dynarray
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assign c.m_bad1 = 2; // <--- Error: continuous class non-static
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// Only one simulator fails on this, probably not legal
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// assign Cls::s_ok1 = 2; // OK: continuous class static
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logic ok_7;
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task mt(output o); // OK: function output
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o <= 1;
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endtask
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always @(posedge clk) begin
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bad_auto4 <= 2; // <--- Error: nonblocking automatic
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bad_dyn6 <= empty_dyn; // <--- Error: nonblocking dynarray
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Cls::s_ok2 <= 2; // OK: nonblocking class static
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c.m_bad2 <= 2; // <--- Error: nonblocking class automatic
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mt(ok_7);
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$stop;
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end
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endmodule
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