39 lines
885 B
Systemverilog
39 lines
885 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by PlanV GmbH.
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// SPDX-License-Identifier: CC0-1.0
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class AssocArrayWarningTest;
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rand int bit_index_arr [bit[78:0]];
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rand int logic_index_arr [logic[64:0]];
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constraint c {
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bit_index_arr[79'd66] == 65;
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logic_index_arr[65'd3] == 70;
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}
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function new();
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bit_index_arr = '{79'd66:0};
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logic_index_arr = '{65'd3:0};
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endfunction
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endclass
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module t_constraint_assoc_arr_bad;
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AssocArrayWarningTest test_obj;
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initial begin
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test_obj = new();
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repeat(2) begin
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int success;
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success = test_obj.randomize();
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if (success != 1) $stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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