2018-10-31 01:50:09 +01:00
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// DESCRIPTION: Verilator: Verilog Test module
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//
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2020-03-21 16:24:24 +01:00
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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2018-10-31 01:50:09 +01:00
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// Make sure type errors aren't suppressable
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// verilator lint_off WIDTH
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module t(ref int bad_primary_ref
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/*AUTOARG*/);
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endmodule
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