31 lines
741 B
Systemverilog
31 lines
741 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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process job[] = new [8];
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bit is_alloc = 0;
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initial begin
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foreach (job[j]) fork
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begin
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$write("job started\n");
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job[j] = process::self();
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end
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join_none
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foreach (job[j]) begin
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is_alloc = !!job[j];
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wait (is_alloc);
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end
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$write("all jobs started\n");
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foreach (job[j]) begin
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job[j].await();
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end
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$write("all jobs finished\n");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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