47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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`define signal(name, width) wire [width-1:0] name;
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module t (
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`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py
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rand_a, rand_b, srand_a, srand_b
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);
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`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py
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input rand_a;
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input rand_b;
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input srand_a;
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input srand_b;
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wire logic [63:0] rand_a;
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wire logic [63:0] rand_b;
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wire logic signed [63:0] srand_a;
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wire logic signed [63:0] srand_b;
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`signal(CONCAT_RHS, 2);
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assign CONCAT_RHS[0] = rand_a[0];
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assign CONCAT_RHS[1] = CONCAT_RHS[0];
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`signal(CONCAT_LHS, 2);
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assign CONCAT_LHS[0] = CONCAT_LHS[1];
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assign CONCAT_LHS[1] = rand_a[1];
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`signal(CONCAT_MID, 3);
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assign CONCAT_MID[0] = |CONCAT_MID[2:1];
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assign CONCAT_MID[2:1] = {rand_a[2], ~rand_a[2]};
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`signal(SEL, 3);
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assign SEL[0] = rand_a[4];
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assign SEL[1] = SEL[0];
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assign SEL[2] = SEL[1];
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`signal(EXTEND_SRC, 5);
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assign EXTEND_SRC[0] = rand_a[3];
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assign EXTEND_SRC[3:1] = 3'(EXTEND_SRC[0]);
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assign EXTEND_SRC[4] = EXTEND_SRC[1];
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endmodule
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