2024-09-08 13:00:03 -04:00
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#!/usr/bin/env python3
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2006-08-26 11:35:28 +00:00
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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2026-01-26 20:24:34 -05:00
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of either the GNU Lesser General Public License Version 3
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# or the Perl Artistic License Version 2.0.
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# SPDX-FileCopyrightText: 2024 Wilson Snyder
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2020-03-21 11:24:24 -04:00
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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2006-08-26 11:35:28 +00:00
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2024-09-08 13:00:03 -04:00
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import vltest_bootstrap
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2018-05-07 20:42:28 -04:00
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2024-09-08 13:00:03 -04:00
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test.scenarios('simulator')
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test.top_filename = "t/t_interface_array2.v"
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2006-08-26 11:35:28 +00:00
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2025-06-06 12:28:29 +02:00
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test.compile(timing_loop=True, v_flags2=["--coverage --timing"])
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2006-08-26 11:35:28 +00:00
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2024-09-08 13:00:03 -04:00
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test.execute()
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test.passes()
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