2020-01-12 10:03:17 +01:00
|
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
|
|
|
|
//
|
2026-01-27 02:24:34 +01:00
|
|
|
// This file ONLY is placed under the Creative Commons Public Domain.
|
|
|
|
|
// SPDX-FileCopyrightText: 2019 Stefan Wallentowitz
|
2020-03-21 16:24:24 +01:00
|
|
|
// SPDX-License-Identifier: CC0-1.0
|
2020-01-12 10:03:17 +01:00
|
|
|
|
|
|
|
|
`verilator_config
|
|
|
|
|
|
2020-03-21 16:24:24 +01:00
|
|
|
parallel_case -file "t/t_assert_synth.v" -lines 55
|